1. Field
Embodiments of the present invention relate to the fabrication of interconnect structures in microelectronic devices. In particular, embodiments of the present invention relate to utilizing copper to form contact immediately to device formed on a semiconductor substrate.
2. State of the Art
The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the electrical components to form integrated circuits. The metallization patterns are generally referred to as “interconnects.”
One of the main issues confronting the semiconductor processing industry is that of the resistance problem in metallization layers. An industry-wide effort has undertaken to address the problem. Since the beginning, the semiconductor processing industry has relied on aluminum and aluminum alloys to serve as metallization layers. Silicon dioxide was selected as the insulator of choice although polyimide, a polymer, was used in a number of products by IBM for a number of years. With each succeeding generation of technology, the resistance problem grows. Because each generation requires that the dimensions of the semiconductor structure be reduced, the minimum line-space combination must also decrease. As the line-space combination decreases, the resistance of the semiconductor structure increases.
Copper metallurgy has been proposed as a substitute for aluminum metallurgy as a material for the metallization layers since copper exhibits greater conductivity than aluminum. Yet several problems have been encountered in the development of copper metallurgy. The main issue is the fast diffusion of copper through an insulator, such as silicon dioxide, to form an undesired copper oxide compound. Another issue is the known junction-poisoning effect of copper. These issues have led to the development of a liner to separate the copper metallization layer from the insulator.
Suitable liners include titanium nitride, tantalum nitride, tungsten silicon nitride, zirconium, hafnium, titanium, tantalum, and the like.
FIG. 1A illustrates a conventional semiconductor structure 100 (e.g., a transistor). The semiconductor structure 100 includes a substrate 102 having formed therein isolation regions (Shallow Junction Isolation, STI) 104. Active or passive devices can be formed on the substrate 102. Such devices typically include source and drain regions 106, gate dielectric 112, gate electrode 114, spacers 110 and silicide surfaces 108 and 116. As shown in FIG. 1B, to electrically connect to and from the device, contacts 120 (first contacts) are made to the device. Typically, several layers of interconnections are also made to connect to the first layer of contacts. An interlayer dielectric layer 118 is formed and patterned on the substrate 102. Through vias (or contact holes) are formed in the dielectric layer 118 to expose contact areas on the substrate. Contact areas typically are source/drain regions and/or on top of the gate electrode 114. To establish/enhance the contact connection, silicide layers 108 and 116 are formed on the surface of these regions as shown in FIGS. 1A-1B. The through vias are then filled with tungsten (referred to as tungsten plug) to form the first level of contact to the device. In some applications, an additionally contact 122 (or VIA0) formed in a dielectric layer 124 is also formed to connect the contact or tungsten plug 120. The additional contact (or VIA0) 122 can be filled with copper. Then, a plurality of metallization layer 130 having dielectric material 126 and conductive lines 128 are formed on top of the device.
Because of the undesirable characteristics of copper, copper has not been used in forming the first contact that is immediate to the device. However, as devices are scaled smaller and smaller, the high resistivity characteristic of the conductive material such as tungsten that is typically used in the first contact layer is becoming more undesirable. Tungsten causes parasitic resistance in the device by introducing high resistivity and low conductivity at the first contact level, at the junction from the first contact level to other interconnection levels in the devices. Thus, there is a need for a first layer of contact directly to the device that will lower resistivity overall.